RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 309

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
This register contains the interrupt enables that correspond to the status bits in the HOST_ISTAT0 register. The
assertion of the HRST* system reset pin will clear all of the HOST_IMASK0 interrupt enables.
28234-DSH-001-B
0x1d0 - Host Interrupt Mask Register 0 (HOST_IMASK0)
25-24
21-19
14-12
8-4
Bit
31
30
29
28
27
26
23
22
18
17
16
15
11
10
9
3
2
1
0
Field
Size
1
1
1
1
1
1
2
1
1
3
1
1
1
1
3
1
1
1
5
1
1
1
1
EN_PFAIL
EN_PHY_INTR
Reserved
EN_HOST_MBOX_WRITTEN
EN_LP_MBOX_READ
Reserved
Reserved
Reserved
EN_HSTAT1
Reserved
EN_GFC_LINK
EN_RSM_RUN
EN_RSM_HS_WRITE
EN_RSM_LS_WRITE
Reserved
EN_SEG_RUN
EN_SEG_HS_WRITE
EN_SEG_LS_WRITE
Reserved
EN_AAL5_DSC_RLOVR
EN_CELL_DSC_RLOVR
EN_CELL_RCVD_RLOVR
EN_CELL_XMIT_RLOVR
Name
Mindspeed Technologies
Enables interrupt when PFAIL status is a logic 1.
Enables interrupt when PHY_INTR status is a logic 1.
Set to zero.
Enables interrupt when HOST_MBOX WRITTEN status is a logic 1.
Enables interrupt when LP_MBOX_READ status is a logic 1.
Set to zero.
Set to zero.
Set to zero. Reserved for future status page expansion.
Global interrupt enable for HOST_ISTAT1 status register. Individual
interrupts in HOST_ISTAT1 are enabled in HOST_IMASK1.
Set to zero.
Enables interrupt when GFC_LINK status is a logic 1.
Enables interrupt when RSM_RUN status is a logic 1.
Enables interrupt when RSM_HS_WRITE status is a logic high.
Enables interrupt when RSM_LS_WRITE status is a logic high.
Set to zero.
Enables interrupt when SEG_RUN status is a logic high.
Enables interrupt when SEG_HS_WRITE status is a logic high.
Enables interrupt when SEG_LS_WRITE status is a logic high.
Set to zero.
Enables an interrupt when AAL5_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_DSC_RLOVR status is a logic high.
Enables an interrupt when CELL_RCVD_RLOVR status is a logic high.
Enables an interrupt when CELL_XMIT_RLOVR status is a logic high.
™
Description
13.6 Counters and Status Registers
13.0 RS8234 Registers
13-27