RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 81

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Figure 4-1. Segmentation VCC Table
28234-DSH-001-B
(SEG_VBASE(SEG_VCCB)<<5)
Identification
4.2.1.2 VCC
Base Register
VCC_INDEX = 0xFFFD
VCC_INDEX = 0x1000
classes. This includes a default ATM header, which the host may modify during
the segmentation process. See
segmentation VCC Table entry.
The host allocates a region of SAR shared memory for the segmentation VCC
Table at system initialization, based on the maximum number of connections and
the maximum number of ABR connections. The host informs the SAR of the
location of the table through the internal base register, SEG_VBASE
(SEG_VCCB).
entries in the table. The host describes the SEG VCC by initializing the SEG VCC
Table entry including the SCH_STATE portions of the assigned VCC. The
VCC_INDEX, defined as the offset into the table in 10-word increments,
uniquely identifies a segmentation channel. In all communication between the
SAR and the host, a VCC_INDEX field specifies a VCC.
(non-ABR VCC)
VCC_INDEX = 0x3
The VCC Table entry contains generic information common to all traffic
Once a table has been established, the host assigns segmentation VCCs to
(ABR VCC)
(CBR VCC)
Mindspeed Technologies
VCC Table Entry
VCC Table Entry
VCC Table Entry
SCH_STATE
SCH_STATE
SCH_STATE
VCC Table
Section 4.3.1
VCC_INDEX = 0x0
}
}
}
}
}
10 Words = 1 Descriptor
7 Words
7 Words
13 Words
3 Words
™
for full details of the structure of a
4.2 Segmentation Functional Description
}
}
2 Descriptors
1 Descriptor
4.0 Segmentation Coprocessor
100074_016
4-3