RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 59

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
RS8234 Logic Diagram (2 of 3)
Processor Mode Select
SAR/ATM Chip Select
Framer Control/Clock
Local Processor Wait
Framer Configuration
Framer Configuration
Transmit Cell Marker
Receive Cell Marker
Receive Data Parity
Write Byte-Enables
Transmit Enable
Self-Test Failed
Receive Enable
Address Strobe
Write not Read
Transmit Flag
Receive Data
Receive Flag
Word Select
Word Select
Bank Select
Bank Select
Burst Last
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
AF12
AE12
AF15
AF16
AC14
AE7
AF7
AC8
AD8
AE8
AF8
AC9
AF9
AD5
AC10
AE11
AD10
AC13
B16
B10
C10
D11
A10
B12
C12
D12
C11
A15
D14
C14
A13
C13
C15
I = Input, O = Output, OD = Open Drain Output
PROCMODE
PADDR1
PADDR0
PBSEL1
PBSEL0
PBE3*
PBE2*
PBE1*
PBE0*
PCS* (PHYCS1*)
PAS*
PBLAST* (PHYCS2*)
PWAIT*
PWNR
PFAIL*
FRCFG1
FRCFG0
TXSOC(TXMARK)
TXCLAV(TXFLAG*)
TXEN*
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RXPAR
RXSOC(RXMARK)
RXCLAV(RXFLAG*)
RXEN*
RXCLK(FRCTRL)
Mindspeed Technologies
The symbol (*) Indicates Active Low
ATM Physical
Interface
Local Bus
Processor
Interface
PDAEN*
TXPAR
PRDY*
PRST*
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
PINT*
™
2.10 Logic Diagram and Pin Descriptions
AD20
AC20
AF19
AE19
AF20
AE20
AF21
AE21
AE16
B13
B15
A16
D15
OD
I/O
O
O
O
O
2.0 Architecture Overview
Transmit Data
Transmit Data Parity
Memory Ready
Data/Address Enable
Reset Output
Interrupt Output
100074_106
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