RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 258

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

10.0 Local Processor Interface
10.6 Standalone Operation
Figure 10-10. RS8234/RS825x Read/Write Functional Timing
10-16
LADDR[13:0]
LDATA[7:0]
SYSCLK
PWAIT*
PRDY*
PWNR
PCS*
PAS*
tA
1, 2 Read Cycle
edge of SYSCLK) the RS825x samples PCS*, PAS*, and PWNR low, indicating
a read cycle. By the next rising edge of SYSCLK at cycle two, the data is output
by the RS825x to be latched by the RS8234. The same procedure occurs for a
write except that at cycle four, PWNR is sampled high. The RS825x then latches
the data to the appropriate internal register on the next SYSCLK rising edge at
cycle five.
1
Figure 10-10
Read Address
Read Data
tD
Mindspeed Technologies
2
shows a read and write RS825x access. At cycle one (the rising
3
ATM ServiceSAR Plus with xBR Traffic Management
tA
4, 5 Write Cycle
Write Address
Write Data
4
™
tD
5
28234-DSH-001-B
6
RS8234
100074_079