RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 349

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 15-7. RS8234 Memory Interface Timing
28234-DSH-001-B
Symbol
NOTE(S):
(1)
(2)
(3)
(4)
(5)
t
t
t
t
t
t
dodmoe
moedoe
t
t
mweov
t
mweov
t
mcsov
t
mcsov
t
mweh
mwrh
moeh
t
t
t
mwel
t
moel
t
mwrl
t
t
t
dod
t
aov
doe
t
aov
dov
dis
dh
wc
See
T = t
Insert one clock cycle for two cycle memory (one wait state).
See
SYSCLK shown for reference only.
rc
w
Figure 15-7
Figure 15-8
s
for single cycle memory (no wait states), T = 2t
READ Cycle Time
LADDR[18:0] Output Valid
MCS[3:0]* Output Valid
MWE* Byte Enables Output Valid
(RAMMODE = 1)
MOE* Low
MOE* High
LDATA Output Disable
LDATA Input Setup
LDATA Input Hold
LDATA Driven by SAR
LDATA Disable to MOE* Low
MOE* High to LDATA Driven
WRITE Cycle Time
MWR*, MWE[3:0]* Width
LADDR[18:0] Output Valid
MCS[3:0]* Output Valid
MWE* Byte Enables Output Valid
(RAMMODE = 1)
LDATA Output Valid
MWE[3:0]* Low
MWE[3:0]* High
MWR[3:0]* Low
MWR[3:0]* High
for waveforms.
for waveforms.
(1)
(1)
Parameter
(4)
( 4)
(4)
(4)
(2)
(1)
(2)
(1)
( 4)
(1)
(1)
(1)
(4)
(2, 4)
(1)
(4)
(1)
(1)
Mindspeed Technologies
(1)
(1)
Memory Write Timing
Memory Read Timing
s
for two cycle memory, (one wait state).
T/2-2
T/2-2
T/2-2
Min
12
by_8 SRAM
T
1
1
1
5
0
0
6
T
1
1
1
1
4 banks of
Max
16
16
10
10
10
17
10
10
10
10
10
7
1
1
15.0 Electrical and Mechanical Specifications
T/2-2
Min
™
11
by_8 SRAM
T
1
1
1
5
0
0
7
T
1
1
1
1
2 banks of
Max
16
10
16
16
8
8
8
8
6
8
8
8
1
1
1 bank of by_8
T/2-2
Min
11
T
1
1
1
5
0
0
8
T
1
1
1
1
SRAM
Max
15
10
16
16
7
7
7
7
6
7
7
7
1
1
15.1 Timing
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15-9