RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 60

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
RS8234 Logic Diagram (3 of 3)
2-28
Memory Address Bus
RAM Mode Select
Memory Data Bus
Test Mode Select
Test Logic Reset
Serial Test Data
EEPROM Data
2X Clock Input
Test Clock
I/O
I/O
I/O
I
I
I
I
I
I
AD25
AC23
AD26
AC25
AB24
N1
P1
P2
P3
R1
R2
R3
R4
T3
T4
U1
U3
U4
V1
V3
V4
W1
W2
W3
Y1
Y2
Y3
Y4
AA1
AA3
AA4
AB1
AB2
AB4
AC1
AC2
AC3
B9
C9
D9
A8
B8
A7
B7
C7
D7
A6
B6
A5
B5
C5
D5
A4
B4
G4
N4
I = Input, O = Output, OD = Open Drain Output
LDATA31
LDATA30
LDATA29
LDATA28
LDATA27
LDATA26
LDATA25
LDATA24
LDATA23
LDATA22
LDATA21
LDATA20
LDATA19
LDATA18
LDATA17
LDATA16
LDATA15
LDATA14
LDATA13
LDATA12
LDATA11
LDATA10
LDATA9
LDATA8
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
LDATA2
LDATA1
LDATA0
LADDR18
LADDR17
LADDR16
LADDR15
LADDR14
LADDR13
LADDR12
LADDR11
LADDR10
LADDR9
LADDR8
LADDR7
LADDR6
LADDR5
LADDR4
LADDR3
LADDR2
RAMMODE
CLK2X
TRST*
TCLK
TMS
TDI
SDA
Mindspeed Technologies
The symbol (*) Indicates Active Low
Boundary Scan
Serial EEPROM
Clocks/Status
Test Signals
Local Bus
Interface
Memory
ATM ServiceSAR Plus with xBR Traffic Management
LADDR1
LADDR0
SYSCLK
MWE3*
MWE2*
MWE1*
MWE0*
MCS3*
MCS2*
MCS1*
MCS0*
CLKD3
STAT1
STAT0
MWR*
MOE*
TDO
SCL
™
AC24
AB23
M2
L2
F2
F1
J2
J1
K4
K3
H1
G3
G2
H3
H2
J4
C4
A3
O
O
O
O
O Memory Address Bus
O Memory Address Bus
O
O
O SAR Status
O SAR Status
O
O
Memory Bank Chip Selects
Memory Read Enable
Memory Write Enables
Write Enable for by_16 RAM
System Clock Output
Divide by 3 Clock Output
Serial Test Data
EEPROM Clock
28234-DSH-001-B
RS8234
100074_107