RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 250

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

10.0 Local Processor Interface
10.3 Bus Cycle Descriptions
10.3.3 Double Read Burst With Processor Wait States
Figure 10-4. Local Processor Double Read with Wait States Inserted
10-8
LADDR[18:2]
LDATA[31:0]
PADDR[1:0]
LADDR[1:0]
PBSEL[1:0]
MWE*[3:0]
MCS*[3:0]
PBLAST*
SYSCLK
PBE[3:0]
PDAEN*
PWAIT*
D[31:0]
PRDY*
A[20:4]
PWNR
DT/R*
MOE*
PCS*
PAS*
1.
Address
Cycle
ta
10
00
In
allow additional time for the reads to occur. At the rising edge of SYSCLK on
cycle four and cycle six, the combination of PWAIT* low and PRDY* low
extends the read by one more cycle. The local processor word select inputs
(PADDR[1:0]) are latched at cycle one. The RS8234 word select address lines,
LADDR[1:0], are incremented automatically at the beginning of cycle six.
1
2.
Figure 10-4
Arbitration
Cycle
tarb
Mindspeed Technologies
2
3.
the processor inserts wait states on cycle four and cycle six, to
Bus
Recovery
Cycle
tbr
3
4.
tw
Wait
Cycle
A0
A0
ATM ServiceSAR Plus with xBR Traffic Management
4
5.
Data
Cycle
td
1101
™
D0
D0
00
5
6. Wait
Cycle
tw
6
7.
Data
Cycle
td
D1
D1
28234-DSH-001-B
01
7
RS8234
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