RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 139

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
5.6.2 Status Queue Overflow or Full Condition
28234-DSH-001-B
of Status Queue Entries
5.6.1.4 Host Detection
The host can use either a polling operation or an interrupt routine to detect new
status queue entries.
current READ position until it returns a logic high. The host then processes the
status entry, writes the VLD bit to a logic low and increments its current READ
pointer. Periodically, the host writes the current READ index value into the
READ_UD field of the status queue base table entry.
reassembly coprocessor writes a status queue entry into host memory, the
HOST_ISTAT0 (RSM_HS_WRITE) bit is set to a logic high to prompt an
interrupt. Upon receiving an interrupt, the host reads HOST_ST_WR
(RSM_HS_WRITE[15:0]) to determine which host memory status queue(s)
caused the interrupt.
NOTE:
HOST_ISTAT1 upon receiving an interrupt, and periodically read
HOST_ISTAT0 to insure that no error conditions have occurred. Once the
interrupt manager has determined which status queue(s) caused the interrupt, the
host would start reading the appropriate status queues at their current read
location. The host processes status entries until reading an entry with the VLD bit
set to logic low. Again, the host periodically writes the current READ index value
into the READ_UD field of the status queue base table entry.
A status queue overflow or full condition is entered when the last available status
queue entry is written. The reassembly coprocessor detects the condition by
comparing the WRITE+1 and READ_UD index pointers. If the pointers are
equal, a status overflow condition is detected and the RSM coprocessor sets the
internal OVFL bit in the last status queue entry written to a logic high, to indicate
the condition. The RSM coprocessor also sets to one either the RSM_HS_FULL
bit in the HOST_ISTAT1 register, or the RSM_LS_FULL bit in the LP_ISTAT1
register, to prompt an interrupt.
cells. If a COM or EOM cell is received while the status queue is full, the channel
is marked for status full packet discard. When an SSM, EOM, or OAM cell is
received during a status full condition, the cell is discarded and the status queue
checked. If there is now room in the status queue, then the status full condition is
exited.
the user to detect the full condition and advise the peers to check if their queues
have overflowed. Each peer would then check the OVFL bit in the last status
queue entry written (pointed to by READ_UD – 1), to determine if that peer’s
status queue has filled. If the OVFL bit is not set to a logic high, the host should
also check the entry pointed to by (READ_UD – 2) to determine if an overflow
condition occurred during a host update of the READ_UD index pointer. Since
the reassembly coprocessor recovers from the overflow condition automatically,
the host does not have to determine which queue overflowed.
To poll each status queue, the host continuously reads the VLD bit at the
The host can also use an interrupt routine to process status queues. When the
A typical operation for the interrupt manager would be to only read
While the reassembly coprocessor is in status full condition, it discards all
For multiple peer configurations, an interrupt manager can be configured by
Note that only status queues 0–15 are reported in this register.
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5.0 Reassembly Coprocessor
5.6 Status Queue Operation
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