RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 63

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 2-1. Hardware Signal Definitions (3 of 6)
28234-DSH-001-B
FRCFG[1:0]
TXD[7:0]
TXPAR
TXSOC
TXCLAV*
TXEN*
RXD[7:0]
RXPAR
RXSOC
RXCLAV*
RXEN*
RXCLK
Pin Label
Framer Configuration
Transmit Data
Transmit Data Parity
Transmit Cell Marker
Transmit Flag
Transmit Enable
Receive Data
Receive Data Parity
Receive Cell Marker
Receive Flag
Receive Enable
Framer Control/Clock
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
I
I
I
Configuration pins FRCFG[1,0] determine what framer
interface the RS8234 supports.
00 = Reserved, do not use
01 = UTOPIA interface
10 = Slave UTOPIA interface
11 = Reserved, do not use
Carries outgoing data bytes to the framer chip in all framer
modes (8 mA drive).
Outputs the 8-bit odd parity computed over the TxD[7:0] lines
in all framer modes (8 mA drive).
In both UTOPIA and slave UTOPIA modes, the TxSOC line is
asserted by the RS8234 when the starting byte of a 53-byte
cell is being output. (aka TxMark)
In UTOPIA mode, TxClav indicates that the transmit buffer in
the downstream link interface chip is full and no more data
can be accepted. In slave UTOPIA mode, this pin indicates to
the link interface chip that the RS8234 transmit buffer is
empty. (Has pulldown resistor to pull inactive in master mode
when not driven externally.) (aka TxFlag*) (8 mA drive)
TxPar, and TxSOC lines in the current clock cycle when the
RS8234 is in UTOPIA or slave UTOPIA mode. This pin is an
output in UTOPIA mode and an input in slave UTOPIA mode.
(8 mA drive. Has pullup resistor to pull inactive in slave mode
when not driven externally.)
framer chip to the RS8234 in all framer modes.
Should be driven with the 8-bit odd parity computed over the
RXD [7:0] lines by the link interface or framer chip in all
framer modes.
Indicates that the current byte being transferred on the
RxData[7:0] lines is the starting byte of a 53-byte cell. Has
internal pulldown resistor. (aka RxMark)
In UTOPIA mode, RxClav indicates that the receive buffer in
the downstream link interface chip is empty, no more data can
be transferred, and the RxData[7:0], RxPar, and RxSOC lines
are invalid. In slave UTOPIA mode, this pin indicates to the
framer chip that the receive FIFO buffer in the RS8234 is full.
8 mA drive. Has pulldown resistor to pull inactive in master
mode when not driven externally. (aka RxFlag*)
In UTOPIA mode, RXEN* indicates that the RS8234 is ready to
receive data on the RXD[7:0], RXPAR, and RXSOC lines in the
next clock cycle. This pin is an output in UTOPIA mode and an
input in slave UTOPIA mode. Has pullup resistor to pull
inactive in slave mode when not driven externally. 8 mA drive.
In UTOPIA and slave UTOPIA mode, the RXCLK line should be
driven with a clock that is synchronous to that used by the
framer device for interfacing to the RS8234. The TXD[7:0],
TXPAR, TXSOC, TXCLAV*, TXEN*, RXD[7:0], RXPAR, RXSOC,
RXCLAV*, and RXEN* lines must be synchronous to this
clock in UTOPIA mode, and maintain the specified setup and
hold times with reference to its rising edge.
Indicates that valid data has been placed on the TxD [7:0],
Transfers incoming data bytes from the link interface or
™
2.10 Logic Diagram and Pin Descriptions
Definition
2.0 Architecture Overview
2-31