RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 130

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.4 Buffer Management
5-26
5.4.8.5 DMA FIFO Full
The purpose of this function is to allow a graceful recovery from an incoming
DMA FIFO full condition. Without this function the reassembly coprocessor is
stalled when the FIFO is full, until recovery from the full condition. This causes
the cells to be dropped indiscriminately on the upstream side of the reassembly
block without any record of which VCCs the cells belonged to. Upon recovery
from the full condition, cells belonging to corrupted PDUs continue to be
processed, which wastes PCI bandwidth during the recovery phase. This function
provides for a more efficient use of host and SAR resources by allowing the
reassembly block to process and drop cells during the full condition.
condition for subsequent early packet discard. Upon recovery from the full
condition, the reassembly block performs early packet discard on the appropriate
channels as cells are received on those channels. In addition, cells will continue to
be dropped on each channel until after an EOM cell is received for that channel.
Early packet discard processing is delayed until recovery from the full condition,
since the status entry also requires the use of the incoming DMA FIFO.
logic high.
descriptors, and RSM status queues reside in SAR shared memory.
(OAM_FF_DSC) should be set to a logic high.
descriptors, and status queues reside in SAR shared memory.
in the RSM status queue entry being a logic high.
The reassembly block will mark all channels that receive a cell during the full
This function is enabled by setting the FF_DSC bit in each VCC entry to a
The user may want to disable this function if the free buffers, buffer
Similarly, if RSM_CTRL1(OAM_QU_EN) is a logic high, RSM_CTRL1
The user may want to disable this function if the global OAM buffers, buffer
Early packet discard due to a FIFO full condition is indicated by the FFPD bit
entry for this channel will be set to a logic high. The CNT_ROVR bit in the
VCC Table holds this flag information until a status is sent.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234