RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 339

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
Table 14-9. Table of Values for General Control Register Initialization (2 of 3)
28234-DSH-001-B
INT_DELAY
(Interrupt Delay Register)
HOST_ST_WR
(Host Status Write Register)
HOST_ISTAT1
(Host Interrupt Status Register
1)
HOST_ISTAT0
(Host Interrupt Status Register
0)
LP_ISTAT1
(Local Interrupt Status Register
1)
LP_ISTAT0
(Local Interrupt Status Register
0)
HOST_IMASK1
(Host Interrupt Mask Register
1)
HOST_IMASK0
(Host Interrupt Mask Register
0)
LP_IMASK1
(Local Interrupt Mask Register
1)
LP_IMASK0
(Local Interrupt Mask Register
0)
PCI Configuration Space
Register
TIMER_LOC
EN_TIMER
EN_STAT_CNT
STAT_CNT[7:0]
RSM_HS_WRITE
RSM_LS_WRITE
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
(ALL)
COMMAND
LAT_TIMER
BASE_ADDRESS_
REGISTER_0
INTERRUPT_LINE
(ALL OTHER FIELDS)
Mindspeed Technologies
Field
0x8700FC07
0x4040000F
Initialized
0x0346
Value
0x35
0x10
0x01
0x00
0x0
0x0
—
—
—
—
—
—
—
0
0
1
™
14.0 SAR Initialization - Example Tables
Interrupt hold-off timer used with HINT*.
Disable status queue interrupt timer delay.
Enable status queue interrupt counter delay.
Interrupt delay counter set to 53.
Read twice after SAR reset.
Read twice after SAR reset.
Read twice HOST_ST_WR reset.
Read twice HOST_ISTAT1 reset.
Read twice SAR reset.
Read twice LP_ISTAT1 reset.
Enable interrupts in errors, counter
relievers and framer interrupt.
Local processor not used.
Local processor not used.
Enable all functions of PCI interface.
Latency timer = 16 clock periods.
Base address of SAR device in PCI memory
space is 0x0100_0000.
Interrupt vector = 0.
Hard-coded reads only.
Enable all errors to cause an interrupt.
Notes
14.4 General Initialization
14-17