RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 54

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.6 Burst FIFO Buffers
Figure 2-10. Data FIFO Buffers
2-22
PCI
2.6 Burst FIFO Buffers
To conserve local memory bandwidth, the RS8234 does not use its local SRAM
as a buffer for incoming or outgoing data. Instead, the RS8234 uses six dedicated
internal FIFO data buffers as follows:
Figure 2-10
Burst FIFO Buffer
Data FIFO Buffer
DMA Slave Read
DMA Slave Write
DMA Master Read
Burst FIFO Buffer
DMA Master Write
Burst FIFO Buffer
• Two DMA master burst FIFO buffers (read =16 words; write=512 words.
• Two DMA slave burst FIFO buffers, (read = 8 words and write = 64
• One FIFO buffer between the PHY interface and the segmentation coprocessor
• One FIFO buffer between the PHY interface and the reassembly
Command +
PCI Master
PCI Slave
words).
( 1 to 9 cells) . See
coprocessor (64 words).
512
64
8
16
Mindspeed Technologies
illustrates the data FIFO buffer.
Segmentation
Reassembly
Section
Controller
Controller
ATM ServiceSAR Plus with xBR Traffic Management
4.2.4.
Interface FIFO
Interface FIFO
Transmit PHY
Receive PHY
™
1 to 9 Cells
64
Interface
PHY
28234-DSH-001-B
RS8234
8236_097