RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 325

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
14.1.2 Segmentation Internal Memory Control Structures
28234-DSH-001-B
Table 14-2. Table of Values for Segmentation Internal Memory Initialization
SEG_SQ_BASE Table
Entry 0
(SEG Status Queue
Base Table Entry 0)
SEG_TQ_BASE Table
Entry 0
(SEG Transmit Queue
BAse Table Entry 0)
Table
BASE_PNTR
LOCAL
SIZE
WRITE
READ_UD
Rsvd
READ_UD_PNTR
LOCAL
UPDATE
READ
Rsvd
Before segmentation is enabled, the host must allocate and initialize all of the
segmentation internal memory control structures.
value(s) for each field.
Field
Mindspeed Technologies
Initialized Value
0x1C00
0x40
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
0
Base address of status queue 0 is 0x1C00.
Status queue 0 resides in host memory.
Size of status queue 0 is 64 entries.
Must be initialized to zero.
Must be initialized to zero.
Must be initialized to zero.
READ_UD located in host memory.
Must be initialized to zero.
Must be initialized to zero.
Must be initialized to zero.
Location of READ_UD is at 0x100.
™
14.0 SAR Initialization - Example Tables
Table 14-2
14.1 Segmentation Initialization
Notes
lists the initial
14-3