RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 90

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

4.0 Segmentation Coprocessor
4.2 Segmentation Functional Description
4.2.5 Status Reporting
4.2.6 Virtual FIFOs
4-12
The RS8234 informs the host of segmentation completion using segmentation
status queues. The host assigns each VCC to one of 32 status queues, enabling a
multiple peer architecture as described in
entry on either PDU or buffer boundaries, selectable on a per-VCC basis by
setting the STM_MODE bit. PDU boundary status is referred to as Message
Mode, while buffer status reporting is called Streaming Mode. Error conditions
also generate status queue entries, though this is a rare occurrence within a
RS8234 subsystem’s segmentation block. The segmentation status queues operate
according to the write-only host interface, defined in
associated with the status entry. The SAR does not use this field for any internal
purpose; it simply circulates the information back to the host. The value of
USER_PNTR must uniquely describe the segmented buffer associated with the
SBD. USER_PNTR may contain the address of the buffer or of a host data
structure describing the buffer. To simplify host management, the RS8234 also
returns the VCC_INDEX of the VCC on which the buffer was transmitted.
In addition to gathering PDU data from buffers, the RS8234 provides an optional
method to segment from a fixed PCI address, or Virtual FIFO. The RS8234
supports AAL0, CBR Virtual FIFO segmentation.
CURR_PNTR and RUN fields to zero in the SEG VCC Table entry. The host
writes the FIFO address to the FIFO_PNTR field in the VCC Table entry. The
host also initially sets the SCH_MODE field = CBR.
Once the FIFO is almost full, the host sets the RUN bit to a logic high. The SAR
will then start reading from the FIFO. When the FIFO gets below almost empty,
the host will set the SCH_OPT bit to a logic high. The SAR will then skip a cell
transmit opportunity in order to allow the FIFO to refill. After the SAR skips a
cell, it will reset the SCH_OPT bit to a logic low.
host FIFO, and prepends (i.e., attaches to the beginning) the ATM_HEADER
value in the VCC Table entry. The host does not use the transmit queue for Virtual
FIFOs. The RS8234 transmits cell payloads from this location indefinitely, with
no status reporting.
The RS8234 returns a user supplied field (USER_PNTR) from the first SBD
The host configures the channel for Virtual FIFO operation by setting the
At this point, the host can start writing cells to the external host transmit FIFO.
In this mode, the segmentation coprocessor reads 48 bytes of payload from the
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
Section
3.2. The RS8234 reports status
Section
3.3.2.
28234-DSH-001-B
RS8234