RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 286
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RS8234EBGC
Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234EBGC.pdf
(401 pages)
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13.0 RS8234 Registers
13.2 System Registers
13.2 System Registers
0x00 - Real-Time Clock Register (CLOCK)
This register contains the 32-bit real time clock. It is incremented by the system clock (SYSCLK), which has
been divided by the DIVIDER[6:0] field in the CONFIG0 register. It can be written to any value by each
processor, and can generate an interrupt on the RTC_OVFL status bit in the LP_ISTAT0 register when it
overflows from 0xFFFFFFFF to 0x0.
0x04 - Alarm Register 1 (ALARM1)
This register contains a 32-bit value which is compared against the CLOCK register. When the two registers are
equal, the ALARM1 status bit in the LP_ISTAT0 register is latched and can be enabled to cause an interrupt to
the local processor. To implement a periodic interrupt, add a constant value to this register after each interrupt.
13-4
31–0
31–0
Bit
Bit
Field
Size
Field
Size
32
32
CLOCK[31:0]
ALARM1[31:0]
Name
Name
Mindspeed Technologies
Real-time clock value.
ALARM1 comparison value.
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
Description
28234-DSH-001-B
RS8234
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