RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 292

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

13.0 RS8234 Registers
13.3 Segmentation Registers
0x8c - Segmentation Transmit Queue Base Register (SEG_TXBASE)
The SEG_TXBASE register sets the base address in SAR shared memory for the transmit queues and enables
the individual queues. The base address is 128-byte aligned and only the 16 most significant bits of the address
are specified in the SEG_TXBASE register.
13-10
31-16
15-13
12-5
4-0
Bit
Field
Size
16
3
8
5
SEG_TXB[15:0]
Reserved
XMIT_INTERVAL[7:0]
TX_EN
Name
Mindspeed Technologies
Base address for the transmit queues.
Program and read as zero.
Interval for transmit queue READ_UD_PNTR update.
Transmit queues 0-TX_EN are enabled.
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
28234-DSH-001-B
RS8234