RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 135

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
5.4.11.3 Credit Return
The user returns credit, at the same time the buffer is recovered to the free buffer
queue, by writing the third word of the free buffer queue. The VCC_INDEX is
written to the channel to which credit is returned. The FWD_VLD bit is set to a
logic high, and the QFC bit is set to a logic low. The RSM coprocessor increments
the RX_COUNTER[15:0] of the applicable channel. For proper operation of the
update interval function, buffers must be returned at the same time as credits are
returned.
return buffer credits independently from buffer usage, the RS8234 maintains a
separate read pointer into free buffer queues that return credits. This pointer name
is FORWARD, in the free buffer queue base table entry. The host determines the
number of Bank 0 free buffer queues that return credits by setting FWD_EN in
the RSM_FQCTRL register.
When a write completes, the RS8234 will begin processing firewall return credits
on that queue. The third word of each entry will be read, and if FWD_VLD is set,
a credit will be added to the VCC_INDEX indicated. The RS8234 will continue
to process credit return entries until FWD_VLD is zero. Multiple free buffer
queues might have credit return entries outstanding at one time. The RS8234 will
process the entries according to the priority set in FWD_RND in the
RSM_FQCTRL register. If FWD_RND is a logic low, the RS8234 will exhaust
the credit returns on the highest number active queue before proceeding to other
queues. Otherwise, it will service the queues in round-robin order.
FORWARD read pointer to the first entry where credit will be returned. Typically,
this will be the first entry after the initial buffers placed on the queue.
5.5 Global Statistics
To meet the requirements of ILMI (ATM Forum) and AToM (RFC1695)
documents, three register based counters are implemented. They are:
16-bit counter. All three are set to zero upon a reset and are not reset to zero upon
a read of the counter by the host. The counters roll over and optionally cause an
interrupt upon rollover.
Credits are returned to VCCs through Bank 0 free buffer queues. In order to
The RS8234 “snoops” writes to free buffer queues that return firewall credits.
Before the reassembly coprocessor is enabled, the host must initialize the
• CELL_RCVD_CNT - Number of cells received that map to active
• CELL_DSC_CNT - Number of cells received that map to inactive
• AAL5_DSC_CNT - Number of AAL5 CPCS-PDU’s discarded due to per
The first two counters are implemented as 32-bit counters, and the third is a
channels.
channels. This includes idle cells, since those channels will be turned off.
channel firewall, buffer queue underflow, FIFO full packet discard, status
queue overflow, or maximum CPCS-PDU length exceeded on non-EOM
cells.
Mindspeed Technologies
™
5.0 Reassembly Coprocessor
5.5 Global Statistics
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