RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 96
RS8234EBGC
Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234EBGC.pdf
(401 pages)
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Table 4-10. MISC_DATA Field Bit Definitions with HEADER_MOD Bit Set
4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
4.3.2 Data Buffers
4.3.3 Segmentation Buffer Descriptors
Table 4-9. Segmentation Buffer Descriptor Entry Format
4-18
NOTE(S):
not = AAL3/4; used when generating OAM cells.
NOTE(S):
(1)
(2)
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
0
Def.
Bit
1
2
3
4
(1)
(2)
This version of word 0 is used for AAL5 and AAL0 VCCs.
This version of word 0 is used for AAL3/4 VCCs.
This definition of bits 31:16, MISC_DATA field, applies when the HEADER_MOD bit is set, RPL_VCI=0, and AAL_MODE is
31
BASIZE_H
GFC_DATA
30
UU
29
MISC_DATA
28
Data buffers contain CPCS-SDUs for segmentation and reside in host or SAR
shared memory. The RS8234 retrieves host data buffers from any byte aligned
PCI address using the “READ Multiple” PCI command. SAR shared data buffers
must be aligned on word boundaries. Buffers contain any number of bytes of only
user data, up to a maximum of 64 KB.
SBDs reside in SAR shared memory on word aligned addresses. The host
controls the allocation and management of SBDs. For each buffer to be
segmented, the host uses one buffer descriptor from its pool of free descriptors.
for the SBDs.
Table 4-9
27
Rsvd
Mindspeed Technologies
26
through
25
Table 4-13
BUFFER_PNTR
USER_PNTR
24
ATM ServiceSAR Plus with xBR Traffic Management
23
describe the entry formats and field definitions
NEXT_PNTR
NEXT_PNTR
22
™
PTI_DATA
21
SEG_VCC_INDEX
LENGTH
20
19
28234-DSH-001-B
VCI_DATA
18
17
RS8234
Rsvd
Rsvd
16
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