RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 84

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

4.0 Segmentation Coprocessor
4.2 Segmentation Functional Description
Figure 4-3. Before SAR Transmit Queue Entry Processing
4-6
SAR Transmit Queue
HOST WRITE
Processing
(VLD = 1)
SEG VCC Table Entry (VCC_INDEX = 4)
Transmit Queue Entry
1
buffer descriptor chain to the VCC Table entry identified by the VCC_INDEX in
the first SBD. The VCC Table entry includes pointers to buffer descriptors for
segmentation. The SAR will link the new SBDs to the current chain of SBDs on a
VCC. The host can submit data to a VCC while the SAR is segmenting a
previously submitted message. Once the chain has been linked, the RS8234 resets
the transmit queue VLD bit to zero.
Figure 4-3
entry.
NOTE:
CURR_DESCR
LAST_DESCR
VCC STATE
In either case, the SAR services one transmit queue entry by linking the new
BD_PNTR
Note that as the new buffers are submitted, the VCC is processing a single
buffer PDU (BOM/EOM). The RS8234 accepts new PDUs while it is
processing outstanding buffers.
Mindspeed Technologies
and
Figure 4-4
illustrate the process of linking SBDs to a VCC Table
ATM ServiceSAR Plus with xBR Traffic Management
™
BUFF_PNTR = &A
BUFF_PNTR = &B
BUFF_PNTR = &C
BUFF_PNTR = &Z
VCC_INDEX = 4
VCC_INDEX = 4
VCC_INDEX = 4
VCC_INDEX = 4
<BOM/EOM>
CONTROL
CONTROL
CONTROL
CONTROL
(NULL)
(NULL)
<BOM>
<COM>
<EOM>
NEXT
NEXT
NEXT
NEXT
SBDs
28234-DSH-001-B
RS8234
100074_018