RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 198

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

Table 6-6. CBR_TUN_ID Field, Bit Definitions — CBR Slot
Table 6-7. CBR_TUN_ID Field, Bit Definitions — Tunnel Slot
6.0 Traffic Management
6.5 Traffic Management Control and Status Structures
6.5.1 Schedule Table
6.5.2 CBR-Specific Structures
6-38
Table 6-5. Schedule Slot Entry — CBR/Tunnel Traffic
NOTE(S):
(1)
(2)
1-7
Word
6.5.2.2 Tunnel Traffic
Word one is present only when the DBL_SLOT field in SEG_CTRL is set and USE_SCH_CTRL is not asserted, meaning two
words per schedule slot.
When USE_SCH_CTRL is asserted, the value of SLOT_DEPTH determines how many additional words are used in each
schedule slot; from 0 to 7 additional words.
Def.
Def.
0
(1)(2)
Bit
Bit
6.5.2.1 CBR Traffic
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31
31
1
0
30
30
29
29
PRI3
6.5 Traffic Management Control and Status
Structures
At initialization, all words in the entire Schedule Table space should be written to
0xFFFFFFFF. Individual schedule slot entries can then be initialized as either
CBR slots or Tunnel slots as needed. The two formats are displayed in
A schedule slot is dedicated to a CBR connection by formatting the CBR bit to a
logic high and the CBR_TUN_ID field in the slot entry as illustrated in
A schedule slot is dedicated to a CBR tunnel by formatting the CBR bit to a logic
low and the CBR_TUN_ID field of the slot entry as illustrated in
Schedule Slot field descriptions are detailed in
CBR_TUN_ID
28
28
27
27
Mindspeed Technologies
(Reserved for 2 16-bit VBR/ABR pointers)
26
26
25
25
PRI2
CBR_VCC_INDEX (15 bits)
24
24
ATM ServiceSAR Plus with xBR Traffic Management
23
23
22
22
™
(Reserved for 1 VBR/ABR pointer)
21
21
Table
PRI1
20
20
6-8.
19
19
28234-DSH-001-B
18
18
Table
PRI0
Table
17
17
Table
6-7. The
RS8234
6-5.
16
16
6-6.