RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 259

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
10.7 System Clocking
The RS8234 derives all of its timing from a 2x clock input, CLK2X. This clock is
internally divided by two to create the system clock, SYSCLK. This system clock
is used internal to the device, and is output to the system to provide the clock to
an external processor or PHY device. All processor interface signals are
synchronous to SYSCLK.
clock), is provided, and can be used as the clock for the UTOPIA ATM physical
interface. The clock signal would be looped externally to RXCLK (aka
FRCTRL). For example, if CLK2X is 66 MHz, then CLKD3 is 22 MHz, and is
suitable for the UTOPIA interface. If CLK2X is 50 MHz, then SYSCLK is 25
MHz and is suitable for the UTOPIA interface.
physical line rate, number of VCCs, active concurrent VCCs, and the SRAM
cycle time.
10.8 Real-Time Clock Alarm
A real-time clock counter and alarm registers are built into the RS8234. This
real-time clock consists simply of a 7-bit prescaler (configured via the DIVIDER
field in the CONFIG0 Register) that accepts the SYSCLK input and outputs a
constant (nominally 1 MHz) pulse train, and a 32-bit read/write counter (the
Real-Time Clock Register [CLOCK;0x00]), that counts the number of pulses
output by the prescaler since the system was initialized. When the prescaler is set
to generate a 1 MHz pulse train, the CLOCK counter counts in 1 s intervals. An
interrupt is generated when the CLOCK counter overflows, i.e., more than 2
pulses have occurred since it was cleared to zero. If this happens, the CLOCK
counter simply wraps around to zero and starts counting over. The control
processor or host software is responsible for noting the overflow.
Register 1 [ALARM1;0x04], which is continuously compared to the Clock
Register. When a match is detected, the corresponding interrupt is generated to
the local or host processors. Either processor can then respond to this interrupt
and reload a new value into the ALARM1 Register.
In addition, CLKD3 (CLK2X asymmetrically divided by three, an output
The CLK2X frequency required for a given application is a function of the
One simple real-time alarm is implemented in the RS8234. This is Alarm
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10.0 Local Processor Interface
10.7 System Clocking
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