RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 251

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
10.3.4 Single Write With One-Wait-State Memory
Figure 10-5. Local Processor Single Write with One Wait State by_16 SRAM
28234-DSH-001-B
LADDR[18:2]
LDATA[31:0]
PADDR[1:0]
LADDR[1:0]
RAMMODE
PBSEL[1:0]
MWE*[3:0]
MCS*[3:0]
PBE*[3:0]
PBLAST*
SYSCLK
PDAEN*
PWAIT*
D[31:0]
PRDY*
A[20:4]
PWNR
MWR*
DT/R*
MOE*
PCS*
PAS*
1.
Address
Cycle
ta
In
memory. There is no arbitration delay. RAMMODE is a logic high, indicating that
by_16 RAM is used. Here the PBE[3:0]* inputs are latched at cycle one, and are
used to select the byte enables that are active during the cycle when MWR* is
active. In this case, the two most significant bits are active, indicating a 16-bit
write to the two most significant bytes.
0011
00
01
Figure
1
2.
Mindspeed Technologies
Arbitration
Cycle
10-5, the local processor performs a single write into one-wait-state
tarb
2
3.
Bus
Recovery
Cycle
tbr
3
™
4.
D0
A0
D0
A0
tw
Wait
Cycle
4
10.0 Local Processor Interface
5.
10.3 Bus Cycle Descriptions
0011
td
Data
Cycle
1110
01
5
100074_074
10-9