RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 64

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (4 of 6)
2-32
PROCMODE
PADDR[1:0]
PBSEL[1:0]
PBE[3:0]*
PCS*
(PHYCS1*)
PAS*
PWNR
PWAIT*
PBLAST*
(PHYCS2*)
PRDY*
PDAEN*
Pin Label
Processor Mode Select
Word Select Inputs
Bank Select Inputs
Write Byte-Enables
SAR Chip Select
ATM PHY Chip Select
(in standalone mode)
Address Strobe
Write/not Read
Processor Wait
Burst Last
ATM PHY Chip Select
(in standalone mode)
Memory Ready
Data/Address Enable
Signal Name
Mindspeed Technologies
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
I
I
I
When grounded, this input selects the local processor mode.
When pulled to a logic high, the standalone mode is selected.
The PADDR[1,0] inputs are connected to the word select field
of the CPU address bus (address bits [3, 2] for the Intel
i80960CA processor, which can perform 4-word burst
transactions). These inputs are used by the RS8234 to allow
single-cycle bursts to be performed without requiring very
short memory access times.
Select one of four banks of memory to be accessed. They are
decoded by the memory controller to generate the appropriate
chip/bank selects to the external memory.
Supplies byte enables for each local processor memory
access. These pins are only relevant during writes by the local
processor to SAR shared memory. Each byte enable line
corresponds to a specific byte lane in the LDATA[31:0] data
bus: PBE[0]* corresponds to LDATA[7:0], PBE[1]* to
LDATA[15:8], PBE[2]* to LDATA[23:16], and PBE[3]* to
LDATA[31:24].
In local processor mode with PROCMODE tied low, PCS* is
the SAR chip select input. In standalone mode, this pin is
PHYCS1*, which may be connected to the chip select input of
the Mindspeed PHY device.
Indicates a local processor address cycle. In standalone
mode, PAS* is used to drive the AS* pin of the Mindspeed
PHY device.
The PWNR input indicates the direction of a local processor
transfer. A logic one indicates a write while a logic zero
indicates a read. During standalone mode, this output
provides the same function for the Mindspeed PHY device.
Used by the local processor or external logic to insert wait
states for read or write transactions.
In local processor mode, this input is used by the processor to
indicate the end of a transaction. During standalone mode,
this output is a second chip select, PHYCS2*.
Signals that the memory or control register has accepted the
data on a write, or that data is available to latch by the local
processor on a read cycle.
Connected to the output enable input of the bidirectional
transceivers and buffers used to isolate the RS8234 data and
address bus from the local processor. In standalone mode,
this input is connected to the physical device’s interrupt
output(s).
ATM ServiceSAR Plus with xBR Traffic Management
™
Definition
28234-DSH-001-B
RS8234