RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 320

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

13.0 RS8234 Registers
13.7 PCI Bus Interface Registers
13-38
PCI Special Status Register
(1)
28-23
22-16
15-12
7-0
Bit
31
30
29
11
10
9
8
May be loaded from EEPROM.
Field
Size
1
1
1
6
7
4
1
1
1
1
8
EN_SID_WR
MSTR_CTRL_SWAP
SLAVE_SWAP
Reserved
Memory Size Mask
Reserved
INTF_DIS
INT_FAIL
MERROR
MRD
Reserved
Name
(1)
(1)
(1)
Mindspeed Technologies
Enable SVID/SID Write. Default=0.
Enable byte swapping on control words that the SAR writes. Default=low.
Enable byte swapping on control words of a slave write or read access.
Default=low.
Set to 0b000000.
A 7-bit mask which sets one of a range of values for the size of the PCI
address space. Default=0000000.
Set to 0x0.
Master Interface Disabled. If the M_EN bit in the COMMAND field is a logic
low, any attempt by the RS8234 to perform a DMA transaction to the PCI
bus will result in an error. INTF_DIS and MERROR bits will both be set to a
logic high. This bit can be reset by writing a logic high to itself.
Master Interface Failed. Set to a logic high when an internal PCI/DMA
synchronization error has occurred. The MERROR bit will also be set to a
logic high. This bit can be reset by writing a logic high to itself.
Memory Error. Indicates that the PCI bus master has encountered a fatal
error and therefore has halted operation. Set when either RTA, RMA, DPR,
INTF_DIS, or INT_FAIL errors occur. This bit can be reset by writing a logic
high to itself.
Error on Master Read/Write. If a logic high, indicates that the errored
transaction was a read and the address of the read is located in the
MASTER_READ_ADDR field. If a logic low, indicates the errored
transaction was a write and the corresponding address is located in the
MASTER_WRITE_ADDR field.
Set to 0x00.
0000000 = 8 M
ATM ServiceSAR Plus with xBR Traffic Management
™
Description
28234-DSH-001-B
RS8234