RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 123

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
5.4.2 Scatter Method
Figure 5-11. Host and SAR Shared Memory Data Structures for Scatter Method
28234-DSH-001-B
The RS8234 uses an intelligent scatter method to write cell payload data to host
memory. During reassembly to host memory, the reassembly coprocessor uses the
DMA coprocessor to control the scatter function. The reassembly coprocessor
controls the incoming DMA block during scatter DMA to host memory.
host memory, one in SAR shared memory, and one in internal memory. The
linked cell buffers (HCELL_BUFF) and reassembly buffer descriptors reside in
host memory, and the free buffer queues (HFR_BUFF_QU) reside in SAR shared
memory. The free buffer queues also have an associated free buffer queue base
table. This table is in internal memory. The RS8234 allows for up to
32 independent free buffer queues.
Four data structures are maintained as illustrated in
Buffer Descriptors
Cell buffers
HOST
Mindspeed Technologies
(Inside the RS8234)
Free Buffer Queues
Free Buffer Queue
SAR-Shared
Base Table
™
5.0 Reassembly Coprocessor
Figure
5.4 Buffer Management
5-11: two in the
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