RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 4

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

Multi-Queue Segmentation Processing
The RS8234’s segmentation coprocessor generates ATM cells for up to 64 K VCCs at a line rate of up to 200 Mbps for
simplex connections. The segmentation coprocessor formats cells on each channel according to segmentation VCC
Tables, utilizing up to 32 independent transmit queues and reporting segmentation status on a parallel set of up to 32
segmentation status queues. The segmentation coprocessor fetches client data from the host, formats ATM cells while
generating and appending protocol overhead, and forwards these to the UTOPIA port. The segmentation coprocessor
operates as a slave to the xBR Traffic Manager which schedules VCCs for transmission.
Multi-Queue Reassembly Processing
The RS8234’s reassembly coprocessor stores the payload data from the cell stream received by the UTOPIA port into
host data buffers. Using a dynamic lookup method which supports NNI or UNI addressing, the reassembly coprocessor
processes up to 64 K VCCs simultaneously. The host supplies free buffers on up to 32 independent free buffer queues,
and the reassembly coprocessor performs all CPCS protocol checks and reports the results of these checks as well as
other status data on one of 32 independent reassembly status queues.
High Performance Host Architecture with Buffer Isolation
The RS8234 host interface architecture maximizes performance and system flexibility. The device’s control and status
queues enable host/SAR communication via write operations alone. This lowers latency and PCI bus occupancy.
Flexibility is achieved by supporting a scalable peer-to-peer architecture. Multiple host clients may be addressed by the
SAR as separate physical or logical PCI peers. Segmentation and reassembly data buffers on the host system are
identified by buffer descriptors in SAR shared (or host) memory which contain pointers to buffers. The use of buffer
descriptors in this way allows for isolation of data buffers from the mechanisms that handle buffer allocation and
linking. This provides a layer of indirection in buffer assignment and management that maximizes system architecture
flexibility.
Designer Toolkit
Mindspeed provides an evaluation environment for the RS8234 which provides a working reference design, an example
software driver, and facilities for generating and terminating all service categories of ATM traffic. This system
accelerates ATM system development by providing a rapid prototyping environment.
Mindspeed Technologies
28234-DSH-001-B
™