RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 5

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

New Features
• 3.3 V, 388 BGA lowers power and
• AAL3/4 CPCS generation and
• PCI 2.1, including support for serial
• Enhancements to xBR Traffic
• Reduced memory size for VCC
• Increased addressing flexibility
• Additional byte lane swappers for
xBR Traffic Management
• TM 4.1 Service Classes
• 16 Levels of priorities (16 + CBR)
• Dynamic per-VCC scheduling
• Multiple programmable ABR
• Scheduler driven by local system
• Internal RM OAM cell feedback path
• Virtual FIFO rate matching (Source
• Per-VCC MCR and ICR.
• Tunneling
Multi-Queue Segmentation Processing
• 32 transmit queues with optional
• 64 K VCCs maximum *
• AAL5 & AAL3/4 CPCS generation
• AAL0 Null CPCS (optional use of PTI
• ATM cell header generation
• Raw cell mode (52 octet)
• 200 Mbps half duplex
• 155 Mbps full duplex (w/ 2-cell
• Variable length transmit FIFO - CDV -
28234-DSH-001-B
eases PCB assembly
checking
EEPROM
Manager
– fewer ABR templates
– improved CBR tunneling
lookup tables
increased system flexibility
– CBR
– VBR (single, dual and CLP-based
– Real time VBR
– ABR
– UBR
– GFC (controlled & uncontrolled
– Guaranteed Frame Rate (GFR)
templates (supplied by Mindspeed or
user)
clock for low jitter CBR
Rate Matching)
– VP tunnels (VCI interleaving on
– CBR tunnels (cells interleaved as
priority levels
for PDU demarcation)
PDUs)
host latency matching (1 to 9 cells)
leaky buckets)
flows)
(guaranteed MCR on UBR VCCs)
PDU boundaries)
UBR, VBR or ABR with an
aggregate CBR limit)
• Symmetric Tx and Rx architecture
• User defined field circulates back to
• Distributed host or SAR shared
• Simultaneous segmentation and
• Per-PDU control of CLP/PTI (UBR)
• Per-PDU control of AAL5 UU field
• Message & streaming status modes
• Virtual Tx FIFO (PCI host)
Multi-Queue Reassembly Processing
• 32 reassembly queues
• 64 K VCCs maximum *
• AAL5 & AAL3/4 CPCS checking
• AAL0
• Early Packet Discard, based on:
• Dynamic channel lookup (NNI or UNI
• Message and streaming status
• Raw cell mode (52 octet)
• 200 Mbps half duplex
• 155 Mbps full duplex (w/ 2-cell
• Distributed host or SAR shared
• 8 Programmable reassembly
• Global max PDU length for AAL5
• Per-VCC buffer firewall (memory
• Simultaneous reassembly and
• Idle cell filtering
• 32 K duplex VCCs
Mindspeed Technologies
– buffer descriptors
– queues
the host (32 bits)
memory segmentation
reassembly
– PTI termination
– Cell count termination
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO full
– Frame relay DE with priority
– LECID filtering and echo
– Per-VCC firewalls
addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signalling address
modes
PDUs)
memory reassembly
hardware time-outs (per-VCC
assignable)
usage limit)
segmentation
threshold
suppression
assignment
™
High Performance Host Architecture
with Buffer Isolation
• Write-only control and status
• Read multiple command for data
• Up to 32 host clients control and
• Physical or logical clients
• Descriptor-based buffer chaining
• Scatter/gather DMA
• Endian neutral (allows data word and
• Non-word (byte) aligned host buffer
• Automatically detects presence of Tx
• Virtual FIFOs (PCI bursts treated as a
• Hardware indication of BOM
• Allows isolation of system resources
• Status queue interrupt delay
Designer Toolkit
• Evaluation hardware and software
• Reference schematics
• Hardware Programming Interface -
Generous Implementation of OAM-PM
Protocols
• Detection of all F4/F5 OAM flows
• Internal PM monitoring and
• Optional global OAM Rx/Tx queues
• In-Line OAM insertion & generation
Standards-Based I/O
• 33 MHz PCI 2.1
• Serial EEPROM to store PCI
• PHY interfaces
• Flexible SAR shared memory
• Optional local control interface
• Boundary scan for board-level testing
• Source loopback, for diagnostics
• Glueless connection to Mindspeed’s
transfer
status queues
– Enables peer-to-peer architecture
control word byte swapping, for both
big and little endian systems)
addresses
data or Rx free buffers
single address)
RS823xHPI reference Source code
(C)
generation for up to 128 VCCs
configuration information
– UTOPIA master (Level 1)
– UTOPIA slave (Level 1)
architecture
ATM physical layer device, the
RS8250