RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 281

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
12.8 Receive Cell Synchronization Logic
The receive cell synchronization logic accepts a stream of octets (together with
error and cell boundary indications) from the receive ATM physical interface and
performs the following functions:
• Maintains a sequence counter that marks the various components of an
• Extracts and discards the HEC byte from each 53-byte ATM cell, leaving
• Formats consecutive 4-byte segments into 32-bit words; thus, the header
• Ensures that a complete cell (exactly 52 bytes) is always written to the
• Sets the RSM_OVFL bit in the HOST_ISTAT0/LP_ISTAT0 registers if an
ATM cell: the 5-byte ATM header, the 1-byte HEC field within the header,
and the 48-byte payload. The sequence counter is also used by the ATM
physical interface to check cell boundary synchronization.
52 bytes of cell data.
forms the first word, the first four bytes of the payload form the next word,
and so on. A total of thirteen 32-bit words are created from each 52-byte
cell after the HEC byte has been removed. The bytes within each word are
left-justified (big-endian format), i.e., the first byte received is the MSB of
the word.
FIFO. If a synchronization error occurs, the FR_SYNC_ERR bit in the
HOST_ISTAT0/LP_ISTAT0 registers is set. The ATM physical interface
attempts to resynchronize with the data stream.
octet could not be transferred due to the receive FIFO being full.
Mindspeed Technologies
™
12.8 Receive Cell Synchronization Logic
12.0 ATM Utopia Interface
12-11