RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 120

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

5.0 Reassembly Coprocessor
5.3 CPCS-PDU Processing
Figure 5-10. AAL0 PTI PDU Termination
5.3.4 ATM Header Processing
5-16
. . .
AALO PDU
5.3.3.2 AAL0 Error
. . .
ATM Cells
Conditions
PTI[0]=0
(Hdr)
(Payload)
Status Queue entry for that channel. See
If the RS8234 receives a non-EOM cell in PTI termination mode, where
with the LEN_ERROR and EPD status bits set. Refer to
on how this process is handled.
underflow, status queue overflow, and per-channel buffer firewall), in the same
way as AAL5 CPCS-PDUs are processed.
ATM level CI and CLP are mapped to the CPCS-PDU status queue entry in the
following manner:
Figure 5-10
The RS8234 reports all PDU termination events, with or without errors, in a
EPD is performed. The RS8234 reports this condition via a status queue entry,
For each EOM cell where
the PDU is completed, with BA_ERROR status bit set.
The RS8234 processes error conditions for AAL0 (such as free buffer queue
• LP: value of the ATM Header CLP bit ORed across all cells in a
• CI_LAST: value of ATM Header PTI[1] bit in last cell of CPCS-PDU.
• CI: value of ATM Header PTI[1] bit ORed across all cells in a CPCS-PDU.
CPCS-PDU.
Mindspeed Technologies
PTI[0]=0
provides an illustration of this.
(Hdr)
TOT_PDU_LEN
TOT_PDU_LEN
(Payload)
ATM ServiceSAR Plus with xBR Traffic Management
+
+
™
Section
48 > CCOUNT
48 > CCOUNT
. . .
. . .
5.6.
PTI[0]=1
(Hdr)
2
2
Section
(EOM Cell)
28234-DSH-001-B
(Payload)
5.4.8, for details
RS8234
100074_031