RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 270

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

11.0 PCI Bus Interface
11.10 PCI Host Address Map
11.9.4 Using the Subsystem ID Without an EEPROM
11-10
For applications that can utilize BIOS or boot code to initialize devices before
loading high-level operating system software, the RS8234 allows for the
programming of the PCI Configuration space fields, SUBSYSTEM_ID and
SUBSYSTEM_VENDOR_ID. This feature allows a user to employ the RS8234
without an EEPROM, but still allowing for unique Subsystem IDs.
BIOS must first write a logic one to bit 31 of the PCI Special Status Register. This
enables the writing to these two fields in the PCI Configuration space. BIOS can
then update the IDs by writing the desired values to the PCI Configuration space
at offset 0x2C. Once the values are written, BIOS should then disable the writing
to these fields by setting bit 31 of the PCI Special Status Register to logic zero.
When bit 31 is set to zero, writes to these two fields are ignored.
11.10 PCI Host Address Map
that seen by the host processor. The base address of the RS8234 resource
mapping is defined in the BASE_ADDRESS_REGISTER_0 field, located in the
PCI configuration space.
the first address. Subsequent data words read during a burst read will be
indeterminate.
To program the SUBSYSTEM_ID and SUBSYSTEM_VENDOR_ID fields,
The address map of the RS8234 resources seen by the PCI bus is the same as
Burst reads of the Control and Status registers will only return valid data for
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234