RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 319

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
PCI Command Register
PCI Status Register
(1)
(1)
15-10
26-25
19-16
5-3
Bit
Bit
31
30
29
28
27
24
23
22
21
20
9
8
7
6
2
1
0
May be loaded from EEPROM.
May be set to zero from EEPROM.
Field
Size
Field
Size
1
1
1
1
1
2
1
1
1
1
1
4
6
1
1
1
1
3
1
1
1
DPE
SSE
RMA
RTA
DPR
NEW_CAP
Reserved
Reserved
FB_EN
SE_EN
Reserved
PE_EN
Reserved
M_EN
MS_EN
(1)
(1)
Name
(1)
Name
Mindspeed Technologies
Set to 0x000.
Master Fast Back-to-back enable across target.
SERR* pin output enable.
Set to zero.
Parity Error detection and report enable.
Set to zero.
Master enable. M_EN must be asserted (i.e., set to one) before the RS8234
can act as master on the PCI bus.
Memory Space enable. MS_EN must be asserted (i.e., set to one) before
the RS8234 address space (registers and memory) can be accessed
across the PCI interface.
I/O Space enable. (Not used.) Set to zero.
Parity Error Detected.
Signalled System Error. (Device asserted SERR*.)
Received Master Abort. (Device Master aborted transfer.)
Received Target Abort. (Detected target abort as master.)
Target aborted as slave.
Devsel Speed (00 Fast).
Reported Data Parity Error. (Parity error detected as master).
Fast Back-to-back supported as Slave. Set to one.
UDF Support. Set to zero.
66 MHz Support. Set to zero.
Capability List Support. This bit indicates whether this function
implements a list of extended capabilities defined in PCI Bus Spec.,
Revision 2.1, such as PCI Power Management. When set to one, indicates
the presence of New Capabilities. A value of 0 indicates that this function
does not implement New Capabilities. Set to one.
Set to 0x0.
™
Description
Description
13.7 PCI Bus Interface Registers
(1)
13.0 RS8234 Registers
13-37