RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 97

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

Table 4-11. MISC_DATA Field Bit Definitions with RPL_VCI BIt Set
Table 4-12. MISC_DATA Field Bit Definitions with AAL_MODE Set to AAL3/4
RS8234
ATM ServiceSAR Plus with xBR Traffic Management
NOTE(S):
activate GFC override, the HEADER_MOD bit must be set to a logic high.
Table 4-13. Segmentation Buffer Descriptor Field Descriptions (1 of 3)
28234-DSH-001-B
NOTE(S):
under a VP VCC.
UU
BASIZE_H
BASIZE_L
NEXT_PNTR
USER_PNTR
BUFFER_PNTR
LOCAL
SET_CI
SET_CLP
HEADER_MOD
Def.
Bit
Def.
Bit
Field Name
This definition of bits 31:16, MISC_DATA field, applies when the RPL_VCI bit is set; used when identifying virtual channels
This definition of bits 31:16, MISC_DATA field, applies when the AAL_MODE field = AAL3/4 and RPL_VCI = 0. In order to
31
31
GFC_DATA
30
30
29
AAL5 User-to-User indication. This field is copied to the VCC Table Entry UU field when BOM is set and
AAL_MODE is AAL5.
The high order bits used for the BASize field in the AAL3/4 header when the GEN_PDU option is
selected.
The low order bits used for the BASize field in the AAL3/4 header when the GEN_PDU option is
selected.
Pointer to next buffer descriptor for the VCC. The two least significant bits of the pointer are assumed
to be zero (word-aligned). The host links segmentation buffer descriptors by writing this field to
[(ADDRESS of SDB)>>2] or [(ADDRESS of SBD)/4] before submitting the chain on the Transmit
Queue. The NEXT_PNTR of the last buffer descriptor in a chain is set to NULL (=0).
User data field returned in status entry. This field may equal BUFFER_PNTR. The SAR circulates this
field back to the host in the status entry without using it internally.
Pointer to segmentation buffer in host or SAR shared memory space. Host or SAR shared memory
location is determined by the LOCAL bit.
0 - BUFFER_PNTR is a byte aligned PCI address.
1 - BUFFER_PNTR is a word aligned address in SAR shared memory instead of host memory.
0 - The RS8234 generates bit 1 of PTI[2:0] from the VCC Table Entry ATM_HEADER field.
1 - Sets bit 1 of the ATM header PTI[2:0] field for all cells in buffer to one.
0 - The RS8234 generates the CLP bit from the VCC Table Entry ATM_HEADER field.
1 - Sets the ATM header CLP bit for all cells in buffer to one.
Also used to control VBR CLP Dual Leaky Bucket mode.
0 - The RS8234 ignores the WR_GFC, WR_PTI, and WR_VCI bits in this buffer descriptor.
1 - Activates the WR_GFC, WR_PTI, and WR_VCI bits for this buffer descriptor.
29
28
28
27
27
Rsvd
Mindspeed Technologies
26
26
25
25
24
24
NEW_VCI
Description
23
23
22
22
™
4.3 Segmentation Control and Data Structures
21
21
BASIZE_L
20
4.0 Segmentation Coprocessor
20
19
19
18
18
17
17
4-19
16
16