RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 163

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
6.1.1 xBR Cell Scheduler
Figure 6-1. Non-ABR Cell Scheduling
28234-DSH-001-B
System
Clock
Cell Scheduler
Parameters
and Priority
Schedule
Per-VCC
Dynamic
Table
xBR
The Cell Scheduler maintains the QoS guarantees for each service category. It
rate-shapes all segmentation traffic according to per-channel parameters. This
provides each channel with appropriate transmission opportunities and guarantees
conformance with network traffic contract policing algorithms applied to the
outputs.
Schedule Table. Schedule Slots in this table may be pre-reserved for CBR
services. The VPs and VCs with CBR service reserve cell slots for transmission,
and are intended for highly regular data sources, such as voice circuits. The
RS8234 schedules all other traffic dynamically. The proprietary dynamic
scheduling algorithm uses the remaining bandwidth to statistically multiplex all
other service classes onto the line. The RS8234 can manage VCC traffic on either
a VC or a VP level. As well, it can schedule traffic as a CBR tunnel (or pipe), i.e.,
several VCCs assigned to a single CBR scheduling priority, with individual VCCs
within that tunnel scheduled based on their traffic parameters. Traffic into this
CBR tunnel can be of types UBR, VBR and ABR. To enhance flexibility, the
RS8234 supports 16 priorities of non-CBR traffic.
flow for CBR, VBR, and UBR traffic. The Cell Scheduler tracks cell slots using
the system clock and decides which VCC should send during each slot. This
decision is based upon per-VCC parameters and the current condition of the
Dynamic Schedule Table. Unlike ABR, these service categories are open loop,
and need no feedback from the network for run-time cell scheduling.
The Cell Scheduler selects individual channels based upon the Dynamic
Figure 6-1
Mindspeed Technologies
VCC_INDEX
shows a high level block diagram of the Cell Scheduler control
Segmentation
Coprocessor
™
CBR
UBR
GFR
VBR
6.0 Traffic Management
Network
ATM
6.1 Overview
100074_040
6-3