RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 213

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
6.5.8 Scheduler Internal SRAM Registers
Figure 6-23. Head and Tail Pointers
28234-DSH-001-B
Table 6-34. RS_QUEUE Field Descriptions
OAM_PM
BLER
SEG_VCC_INDEX
BCK_TUC0
BCK_TUC01
TRCC0
TRCC0+1
ER_FWD
SEG_VCC_INDEX
ER_BCK
BN
CI
NI
ER
Field Name
31
OAM PM backward reporting information ready for transmission.
Block Error Result.
Segmentation VCC index for backward reporting OAM PM cell.
TUC0 field in received forward monitoring cell. Written directly from Forward_RM cell.
TUC01 field in received forward monitoring cell. Written directly from Forward_RM cell.
Total Received Cell Count with CLP=0.
Total Received Cell Count with CLP=0+1.
Forward ER RM cell received.
Segmentation VCC index for transmitted Backward ER RM cell.
Backward ER RM cell received.
Backward Explicit Congestion Notification bit from received RM cell.
Congestion Indication bit from received RM cell.
No Increase bit from received RM cell.
Explicit Cell Rate field from received RM cell.
NOTE:
The following graphic is a layout for the head and tail pointers.
Scheduler SRAM registers are located in the address range 0x1640-00x17FF.
Table 6-35
Head
FOR SAR INTERNAL USE ONLY!
Application program should ignore these registers.
Mindspeed Technologies
describes the memory map of these registers.
16 15
Description
Tail
6.5 Traffic Management Control and Status Structures
™
0
8236_166
6.0 Traffic Management
6-53