RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 222

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

7.0 OAM Functions
7.2 Segmentation of OAM Cells
7.2.1 Key OAM-Related Fields for OAM Segmentation
7.2.2 Error Condition During OAM Segmentation
7-8
7.2.1.1 Segmentation
7.2.1.3 Segmentation
7.2.1.2 Low Latency
Buffer Descriptors
7.2.1.4 F4 Flow
Transmission
Status Queue
Several fields in the SBD entry are used to facilitate segmentation of OAM cells.
For low latency, the LINK_HEAD bit in the transmit queue entry should be set to
a logic high. This tells the RS8234 to link the buffer chain at the head of the
existing chain for the corresponding VCC. This bit is intended for use with the
SEG buffer descriptor’s SINGLE option, to send in-line OAM cells. Only a single
SEG buffer descriptor may be linked to a transmit queue entry when this bit is set.
a partial PDU, to ensure correct segmentation.
The SINGLE bit in the SEG status queue entry should be set to a logic high. This
bit is set if the SINGLE option in the AAL_OPT field of the SEG buffer
descriptor is set. This bit indicates a special buffer is in use, rather than the
normal system-assigned buffers for normal CPCS-PDUs.
For F4 flow operation, a separate VCC Table entry must be configured.
Each OAM cell has a 10-bit Error Detection Code (EDC) field, for storing and
transporting the calculated CRC-10 error detection code results (computed over
the OAM cell information fields, excluding the EDC field). To enable this
CRC-10 function, set the CRC10 bit in the SEG buffer descriptor entry to a logic
high.
• Set the 2-bit AAL_OPT field to SINGLE (value = 01). This enables
• Set the OAM_STAT bit to a logic high. The RS8234 will now report status
• Set the single-bit HEADER_MOD field to a logic one. This activates the
• The VCI_DATA field set to a value of three (segment cell) or four
• The PTI_DATA field set to a value of 100 (segment cell) or 101
• Set the AAL_MODE field to 01 (AAL0).
• Set both BOM and EOM bits to zero.
• Set the CRC10 bit to a logic high.
This bit must also be set if the OAM SBD is placed on the transmit queue after
reading 48 octets from a single buffer to form a single ATM cell.
to the OAM-dedicated OAM_STAT_ID identified in the SEG_CTRL
register, instead of the STAT specified in the SEG VCC Table entry.
WR_PTI and WR_VCI bits in the buffer descriptor, which signal the
RS8234 to overwrite the ATM header PTI and VCI fields for that cell with
the values from the PTI_DATA and VCI_DATA fields. In this way, F4 and
F5 flow OAM cells can be generated by the RS8234.
(end-to-end cell) generates an F4 flow OAM cell.
(end-to-end cell) generates an F5 flow OAM cell.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234