RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 25
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RS8234EBGC
Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet
1.RS8234EBGC.pdf
(401 pages)
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RS8234
ATM ServiceSAR Plus with xBR Traffic Management
List of Figures
28234-DSH-001-B
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 2-9.
Figure 2-10.
Figure 2-11.
Figure 2-11.
Figure 2-11.
Figure 3-1.
Figure 3-2.
Figure 3-3.
Figure 3-4.
Figure 3-5.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 4-6.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
Figure 5-8.
Figure 5-9.
Figure 5-10.
Figure 5-11.
Figure 5-12.
Figure 5-13.
Figure 5-14.
RS8234 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Multiple Client Architecture Supports Up To 32 Clients . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
RS8234 Queue Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Interaction of Queues with RS8234 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Reassembly Buffer Isolation — Data Buffers Separated from Descriptors . . . . . . . . . . . . . 2-6
Segmentation Buffer Isolation — Data Buffers Separated from Descriptors . . . . . . . . . . . . 2-7
Segmentation Status Queues Related to Data Buffers and Descriptors . . . . . . . . . . . . . . . . 2-8
Reassembly Status Queues Related to Data Buffers and Descriptors . . . . . . . . . . . . . . . . . 2-9
Write-Only Control and Status Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Multi-Level Model for Prioritizing Segmentation Traffic. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Data FIFO Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
RS8234 Logic Diagram (1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
RS8234 Logic Diagram (3 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Client/Server Model of the RS8234 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Peer-to-Peer vs. Centralized Memory Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Out-of-Band Control Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Write-Only Control Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Write-Only Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Segmentation VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Segmentation Buffer Descriptor Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Before SAR Transmit Queue Entry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
After SAR Transmit Queue Entry Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
AAL5 CPCS-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
AAL3/4 CPCS-PDU Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Reassembly—Basic Process Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2
Reassembly VCC Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Direct Index Method for VPI/VCI Channel Lookup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
Programmable Block Size Alternate Direct Index Method . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Direct Index Lookup Method for AAL3/4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
CPCS-PDU Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8
AAL5 EOM Cell Processing — Fields to Status Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
AAL5 Processing — CRC and PDU Length Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10
AAL3/4 CPCS-PDU Reassembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
AAL0 PTI PDU Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Host and SAR Shared Memory Data Structures for Scatter Method . . . . . . . . . . . . . . . . . 5-19
Free Buffer Queue Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-21
Data Buffer Structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Data Structure Locations for Status Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
RS8234 Logic Diagram (2 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27
Mindspeed Technologies
™
List of Figures
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