RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 313

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
0x1e4 -Local Processor Interrupt Status Register 1 (LP_ISTAT1)
30-27
23-16
9-3
Bit
31
26
25
24
15
14
13
12
11
10
2
1
0
Field
Size
1
4
1
1
1
8
1
1
1
1
1
1
7
1
1
1
Type
—
—
—
L
E
E
E
E
E
E
E
E
E
E
E
E
PCI_BUS_EROR
Reserved
Reserved
RS_QUEUE_FULL
Reserved
SEG_UNFL
SEG_HS_FULL
SEG_LS_FULL
DMA_AFULL
FR_PAR_ERR
FR_SYNC_ERR
RSM_OVFL
RSM_HS_FULL
RSM_LS_FULL
RSM_HF_EMPT
RSM_LF_EMPT
Mindspeed Technologies
Name
This bit is set if the MERROR bit in the PCI configuration
register is set. The MERROR bit is reset by either writing a
logic 1 to the MERROR bit in the PCI configuration register,
or setting the CONFIG0(PCI_ERR_RESET) bit to a logic
high.
Read as zero.
Set when the incoming DMA burst FIFO becomes almost
full.
Set on the occurrence of a parity error on the reassembly
ATM physical interface.
Set on the occurrence of a synchronization error on the
reassembly ATM physical interface.
Read as zero.
Reassembly/segmentation queue full condition.
Reassembly overflow. Indicates that a cell was lost due to a
FIFO full condition.
Set on the occurrence of a host status queue full condition.
Set on the occurrence of a local status queue full condition.
Set on the occurrence of a host free buffer queue empty
condition.
Set on the occurrence of a local free buffer queue empty
condition.
Read as zero.
Segmentation underflow indicates that a scheduled cell
could not be sent due to lack of PCI bandwidth.
Indicates that the segmentation host status queue is full.
Indicates that the segmentation local status queue is full.
™
Description
13.6 Counters and Status Registers
13.0 RS8234 Registers
13-31