RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 100

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

Table 4-16. Transmit Queue Base Table Entry
4.0 Segmentation Coprocessor
4.3 Segmentation Control and Data Structures
Table 4-15. Transmit Queue Entry Field Descriptions
4-22
Table 4-17. Transmit Queue Base Table Entry Field Descriptions
Word 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
4.3.4.2 Transmit Queue
LINK_HEAD
FIND_CHAIN
SEG_BD_PNTR
READ_UD_PNTR
0
1
Field Name
Field Name
Management
Rsvd
0 - The RS8234 links the new descriptor chain at the end of the existing chain on the VCC.
1 - The RS8234 links the new descriptor chain at the head of the existing chain.
If this bit is set, the buffer must contain data for at least one cell. Only a single buffer descriptor may
be linked to a transmit queue entry when this bit is set.
This bit is intended for use with the buffer descriptor SINGLE option to send in line management cells
with reduced latency.
NOTE: It is mandatory that the SINGLE option is set in the buffer descriptor for any Tx Queue entry
with LINK_HEAD set. To do otherwise may result in corrupted segmentation data.
Indicates the SAR is searching for the end of the buffer descriptor chain.
The host always writes this bit to zero.
Points to the first buffer descriptor in the new buffer descriptor chain. Bits 22:2 of the address are
specified; the two least significant bits of the pointer are assumed to be zero (word-aligned).
Points to READ_UD used by host to prevent queue overflow. The SAR will write its read pointer into
the queue to this address periodically. (See
The transmit queues reside in a single continuous section of SAR shared memory.
During initialization the host configures the number of entries per queue with the
SEG_CTRL(TR_SIZE) field. The size ranges from 64 to 4,096 entries per queue.
The host also selects a priority scheme at initialization with the
SEG_CTRL(TX_RND) bit. Both of these fields are static configurations and
must not be changed during runtime operation.
address of all active transmit queues. This register contains the base address of the
first queue, the number of active queues, and the write-only update interval for all
queues. A set of other internal registers, the Transmit Queue Base Table entries,
track the current state of the queues. Table 4-16 and Table 4-17 below describe
the fields of these queues.
queue.
queue. The transmit queue base table contains all of the queue control variables
except for INTERVAL, which is located in the SEG_TXBASE register.
By initializing the SEG_TXBASE register, the host determines the base
The byte address of any transmit queue entry is given by:
The host manages each transmit queue as an independent write-only control
(SEG_TXBASE(SEG_TXB) 128)
<decoded TQ_SIZE value
Chapter 3.0
Mindspeed Technologies
UPDATE
READ_UD_PNTR
describes the runtime management of a write-only control
+
<entry number> 4
ATM ServiceSAR Plus with xBR Traffic Management
Chapter 2.0
Description
Description
Rsvd
+
<transmit queue number>
™
for details.)
READ
28234-DSH-001-B
RS8234