RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 76

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.3 Write-Only Control and Status
Figure 3-5. Write-Only Status Queue
3-10
READ++
3.3.2.2 Queue
Management
0 0 0 0
UPDATE++
1
1 1 1 1 1 1 1 1
BASE_PNTR
(Base table)
Figure 3-5
all of the variables described in
to the host by writing a status queue entry. After it writes the entry, the RS8234
increments its write pointer (WRITE++). This write also triggers a maskable
interrupt.
queue. The VLD bit in each queue entry enables polling. The SAR sets the VLD
bit equal to one when it writes a status queue entry. The host resets it to zero after
processing an entry.
services an entry, it increments a counter (UPDATE++). When this counter
reaches a host-specified threshold (INTERVAL), the host informs the SAR of its
current queue position by writing READ_UD in the queue’s base table register.
The SAR maintains its own write pointer, WRITE. The RS8234 reports status
The host either responds to this interrupt, or periodically polls the status
The host also maintains a pointer (READ) into the status queue. Each time it
1
1
1 1 1 1 1 1 1 1 1
INTERVAL
UPDATE=
N
Mindspeed Technologies
illustrates the status queue management algorithm. The host initializes
Y
0 0 0 0 0 0 0 0
READ_UD_PNTR=
Update SAR
UPDATE=0
READ
ATM ServiceSAR Plus with xBR Traffic Management
Table
VLD
bit
3-3.
Boundary
PCI Bus
™
READ_UD - 1
READ_UD_PNTR
WRITE =
N
Y
28234-DSH-001-B
Overflow
(Base Table)
(Base Table)
READ_UD
Signal
WRITE++
RS8234
100074_015