RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 284

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RS8234EBGC

Manufacturer Part Number
RS8234EBGC
Description
RS8234EBGC ATM XBR SAR
Manufacturer
Mindspeed Technologies
Datasheet

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13.0 RS8234 Registers
13.1 Control and Status Registers
Table 13-1. RS8234 Control and Status Registers (1 of 2)
13-2
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1c
0x20-0x7c
0x80
0x84
0x88
0x8c
0x90-0x9c
0xa0
0xa4
0xa8
0xac
0xb0
0xb4
0xb8
0xbc
0xc0
0xc4
0xc8–0xeC
0xf0
0xf4
0xf8
0xfC
0x100
0x104
0x108
0x10C–0x15C
0x160
Address
CLOCK
ALARM1
Reserved
SYS_STAT
Reserved
CONFIG0
Reserved
INT_DELAY
Reserved
SEG_CTRL
SEG_VBASE
SEG_PMBASE
SEG_TXBASE
Reserved
SCH_PRI
SCH_PRI_2
SCH_SIZE
SCH_CTRL
SCH_ABR_MAX
SCH_ABR_CON
SCH_ABRBASE
SCH_CNG
PCR_QUE_INT01
PCR_QUE_INT23
Reserved
RSM_CTRL0
RSM_CTRL1
RSM_FQBASE
RSM_FQCTRL
RSM_TBASE
RSM_TO
RS_QBASE
Reserved
CELL_XMIT_CNT
Name
Mindspeed Technologies
R/W
R/W
R/O
R/W
R/W
-
R/W
R/W
R/W
R/W
-
R/WB
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/O
Type
Real Time Clock Register
Alarm Register 1
Not Implemented
System Status Register
Not Implemented
Basic Configuration And Control Register 0
Not Implemented.
Interrupt Delay Register
Not Implemented
Segmentation Control Register
SEG VCC Table and Schedule Table Base Address Register
SEG PM Table and Bucket Table Base Address Register
Segmentation Transmit Queue Base Register
Not Implemented
Schedule Priority Register
Schedule Priority Control Register 2
Schedule Size and Slot Minimum Drain Rate Register
Scheduler Control Register
Maximum ABR VCC_INDEX Register
Schedule ABR Constant Register
ABR Decision Table Lookup Base Register
ABR Congestion Notification Register
PCR Queue Interval 0 and 1 Register
Not Implemented
Reassembly Control Register 0
Reassembly Control Register 1
Reassembly Free Buffer Queue Base Register
Reassembly Free Buffer Queue Control Register
Reassembly Table Base Register
Reassembly Time-out Register
Reassembly/Segmentation Queue Base Address Register
Not Implemented
ATM Cells Transmitted Counter
PCR Queue Interval 2 and 3 Register
ATM ServiceSAR Plus with xBR Traffic Management
Must be set to 0.
Description
28234-DSH-001-B
RS8234

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