RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 56

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.8 Standards-Based I/O
2-24
2.8 Standards-Based I/O
PCI Bus I/O
The PCI bus interface implements the full set of address, data, and control signals
required to drive the PCI bus as a master, and contains the logic required to
support arbitration for the PCI bus. This interface is PCI Version 2.1 compliant.
core to connect to a serial EEPROM. This 128-byte EEPROM is used to store
specific PCI configuration information, loaded into the PCI Configuration space
at reset. This allows several user-configurable features:
ATM PHY I/O
The RS8234’s ATM physical interface communicates with and controls the ATM
link interface device, which carries out all the transmission convergence and
physical media dependent functions defined by the ATM protocol. Two modes of
operation are provided: standard UTOPIA and slave UTOPIA. Standard UTOPIA
mode conforms to the UTOPIA Level 1 standard for an ATM Layer device. Slave
UTOPIA mode reverses the control direction for use in place of a PHY on switch
fabrics.
SAR Shared Memory I/O
To simplify system implementations, the RS8234 integrates a complete memory
controller designed for direct interface to common Static RAMs (SRAMs). The
RS8234’s memory controller operates at 33 MHz and can access up to 8 MB of
SRAM memory. The memory controller also arbitrates access to the internal
control and status registers by the host and local processors. The memory banks
can be configured to a variable number of sizes. All of this affords a wide degree
of flexibility in SAR shared memory architecture.
Local Processor I/O
The Local Processor Interface in the RS8234 allows an optional external CPU to
be directly connected to the device to serve as a local controlling intelligence that
can handle initialization, connection management, overall data management,
error recovery, and OAM functions. The use of a local processor for these
functions allows ATM message data to flow to and from host system memory in a
substantially larger bandwidth, as the local processor is handling the “out of
band” functions described above.
connects to the RS8234 through bidirectional transceivers and buffers for the
address and data buses. This allows the processor fast access to RS8234 memory
and registers, but insulates the RS8234 from processor instruction and data cache
fills. It also allows the processor to control multiple RS8234s or physical devices
if desired.
The PCI bus interface also includes an interface module that allows the PCI
• User control of the size of the memory block for PCI addresses
• Enabling byte swapping of control words across the PCI bus
• Loading of Subsystem ID and Subsystem Vendor ID
The processor interface is “loosely coupled,” meaning that the processor
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234