RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 246

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

10.0 Local Processor Interface
10.3 Bus Cycle Descriptions
10-4
10.3 Bus Cycle Descriptions
Throughout the bus cycle descriptions, “cycle” refers to a single SYSCLK cycle
ending with a rising edge. An arbitration cycle is one in which the memory
requests from the local processor and internal memory consumers are compared,
and the one with the highest priority is granted the memory access on the next
cycle. A memory access that was previously arbitrated might occur on an
arbitration cycle. Once the local processor has successfully acquired the memory
controller, it holds the bus until it is relinquished by the assertion of PBLAST* on
the last data cycle. Therefore, local processor burst transfers will always be
completed, and can theoretically be of arbitrary length. However, in practice,
burst transfers should be limited to four or less. The maximum arbitration delay
for a local processor access is on the order of 20 cycles; however, it will typically
be from one to four cycles. This parameter is heavily influenced by the SYSCLK
frequency, line rate, number of VCCs, idle cell ratio, and SRAM access speed.
Therefore, a system design in which local processor accesses must occur within a
fixed time period is not recommended.
Mindspeed Technologies
ATM ServiceSAR Plus with xBR Traffic Management
™
28234-DSH-001-B
RS8234