RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 234

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

8.0 DMA Coprocessor
8.4 Misaligned Transfers
Figure 8-1. LIttle Endian Aligned Transfer
8-2
Length(# of 32 bit words) = 3
PCI Host Address Space
8.4 Misaligned Transfers
The reassembly and segmentation coprocessors handle data internally on word
addresses. The DMA coprocessor must be capable of handling transfers from the
PCI bus without the same constraint, i.e., with data that is not aligned on word
boundaries. In addition, the length of the transfer is specified in bytes, not 32-bit
words, even though the data bus widths are all 32 bits.
RS8234 specifies a host address with the Least Significant Bits (LSBs) = 00, it is
implied that the data is byte aligned.
would map into the PCI host address space for a little endian system. Selecting
between big and little endian systems is done using the ENDIAN [bit 12] in
Configuration Register 0 [CONFIG0;0x14].
ATM Cell
To facilitate this, byte-switching logic is used within the RS8234. When the
Mindspeed Technologies
0
1
Host Address = 00 from RSM block
2
3
11
3
7
4
10
Bytes
2
6
5
1
5
9
ATM ServiceSAR Plus with xBR Traffic Management
6
0
4
8
7
Figure 8-1
8
0x00
0x04
0x08
™
9
10
Address
11
shows how a byte-aligned address
28234-DSH-001-B
RS8234
100074_063