RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 316

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

0x58–
0x14-
Addr
0x2C
0x3C
0x4C
0x7C
Byte
0x00
0x04
0x08
0x0c
0x10
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x54
13.0 RS8234 Registers
13.7 PCI Bus Interface Registers
13.7 PCI Bus Interface Registers
In accordance with the PCI Bus Specification, Revision 2.1, the SAR PCI bus interface implements a 128-byte
configuration register space. These configuration registers are used by the host processor to initialize, control,
and monitor the PCI bus interface logic. The complete definitions of these registers and the relevant fields
within them are given in the PCI bus specification, and are not repeated here. The implementation of the
configuration space registers in the RS8234 is shown in the table directly below. Descriptions of fields and other
registers within the PCI configuration space are shown in the tables following.
PCI Configuration Register
13-34
31
MAX_LATENCY (0x05)
30
29
PM_DATA
Reserved
28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
SUBSYSTEM_ID (SID)
DEVICE_ID (0x8234)
PM_CAPABILITY
STATUS
CLASS_CODE (0x020300)
HEADER_TYPE (0x00)
MIN_GRANT (0x02)
Mindspeed Technologies
Reserved
Reserved
PCI Configuration Register Layout
BASE_ADDRESS_REGISTER_0
SPECIAL_STATUS_REGISTER
MASTER_WRITE_ADDR
MASTER_READ_ADDR
EEPROM_REGISTER
(0x00000000)
Reserved
Reserved
Reserved
Reserved
ATM ServiceSAR Plus with xBR Traffic Management
INTERRUPT_PIN (0x01)
NEXT_CAP_PTR
LAT_TIMER
™
SUBSYSTEM_VENDOR_ID (SVID)
VENDOR_ID (0x14F1)
9
COMMAND
PMCSR
8
7
CACHE_LINE_SIZE (0x00)
CAPABILITY_PTR (0x50)
28234-DSH-001-B
6
INTERRUPT_LINE
CAPABILITY_ID
REV_ID (0x00)
5
(0x01)
4
RS8234
3
2 1
0