RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 338

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

14.0 SAR Initialization - Example Tables
14.4 General Initialization
14.4.1 General Control Registers
Table 14-9. Table of Values for General Control Register Initialization (1 of 3)
14-16
CONFIG0
(Configuration Register 0)
Register
14.4 General Initialization
Before the SAR is enabled, the host must allocate and initialize all of the general
SAR control registers.
LP_ENABLE
GLOBAL_RESET
PCI_MSTR_RESET
PCI_ERR_RESET
INT_LBANK
PCI_READ_MULTI
PCI_ARB
STATMODE
FR_RMODE
FR_LOOP
UTOPIA_MODE
LP_BWAIT
MEMCTRL
BANKSIZE
DIVIDER
Rsvd
Mindspeed Technologies
Field
Table 14-9
Initialized
Value
ATM ServiceSAR Plus with xBR Traffic Management
0x0
0x0
0x0
0-1
0-1
0x3
1
0
0
0
1
1
0
0
0
0
lists the initial value(s) for each field.
™
Local processor not used.
This must be toggled to a logic high and
back to a logic low after completion of all
initialization, but before RSM and SEG
coprocessors are enabled.
Use GLOBAL_RESET to reset SAR.
Must be initialized to zero.
Should be set to zero during initialization,
but set to one after system reset.
PCI Read Multiple Command used.
Round robin arbitration of internal
read/write PCI master.
Selects BOM sync hardware mode.
Early RSM header processing enabled.
Internal ATM physical interface disabled.
Cell handshake mode selected.
Selects zero wait states between
consecutive data cycles during local
processor.
Selects zero wait states SAR shared
memory.
Divide by 128 selected for CLOCK prescaler.
Must be initialized to zero.
512 KB banks selected.
Notes
28234-DSH-001-B
RS8234