RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 274

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

12.0 ATM Utopia Interface
12.4 UTOPIA Mode Cell Handshake Timing
Figure 12-1. Receive Timing in UTOPIA Mode with Cell Handshake
12-4
RXD/RXPAR
NOTE(S):
(1)
(2)
(3)
RXCLAV
RXSOC
Once a cell transfer is started, RxClav is not sampled until the end of the cell.
RxEN* goes active only if there is room in the FIFO buffer for a complete cell.
RxEN* goes inactive at cell boundaries if the receive FIFO buffer cannot accept another cell.
FRCTRL
RXEN*
(2)
H1
12.4 UTOPIA Mode Cell Handshake Timing
If high, the UTOPIA_MODE bit in the CONFIG0 Register selects cell-level
handshaking. Received data is latched from the RXD[7:0] and RXPAR lines on
the rising edge of FRCTRL, after RXEN* is sampled active (see
The 8-bit odd parity computed over the RXD[7:0] lines is compared to the
RXPAR input. If in error, the FR_PAR_ERR bit is set in the HOST_ISTAT0/
LP_ISTAT0 registers. No data is discarded upon a parity error unless the
RSM_PHALT bit in the RSM_CTRL Register is set to a logic high. If so, the
reassembly coprocessor halts upon a parity error. The RXSOC signals to the
RS8234 the start of cell. The RXCLAV input is the physical layer FIFO empty
signal. When it is active, a complete cell is not present in the physical receive
FIFO. The physical layer device sets RXCLAV inactive when it has a complete
cell to transfer. The RS8234 sets RXEN* to a logic low if it can accept a complete
cell. On the clock cycle after the last octet of a cell is transferred, the RS8234
samples the RXCLAV input. If low, the physical device does not have a cell to
transfer. If RXCLAV is high, the physical device has another cell to transfer and
the RS8234 will immediately start receiving the next cell if it can accept a
complete cell. The FR_RMODE bit in the CONFIG0 Register should be set to a
logic low in this mode.
TXEN* is asserted. TXEN* is only asserted when there is data in the RS8234
transmit FIFO. Simultaneously, the 8-bit odd parity computed over the TXD[7:0]
lines is driven on to the TXPAR output. The TXSOC line is driven by the framer
device to indicate start of cell. If the TXCLAV input is asserted by the framer
device, the framer device is full and another cell is not transmitted to the physical
framer. (See
Transmit data is driven on TXD[7:0] on the rising edge of FRCTRL when
H2
Mindspeed Technologies
Figure
***
(1)
12-2.)
P47
P48
ATM ServiceSAR Plus with xBR Traffic Management
X
™
H1
***
P47
(3)
28234-DSH-001-B
P48
Figure
12-3).
RS8234
100074_080