RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 317

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
28234-DSH-001-B
PCI Configuration Register Field Descriptions
DEVICE_ID
VENDOR_ID
STATUS
COMMAND
CLASS_CODE
REV_ID
HEADER_TYPE
LAT_TIMER
CACHE_LINE_SIZE
BASE_ADDRESS
_REGISTER_0
SUBSYSTEM_ID
(SID)
SUBSYSTEM
_VENDOR_ID (SVID)
CAPABILITY_PTR
MAX_LATENCY
MIN_GRANT
INTERRUPT_PIN
INTERRUPT_LINE
Field Name
16-bit device identifier. Serves to uniquely identify the SAR to the host operating system. Set to
0x8234.
16-bit vendor identifier code, allocated on a global basis by the PCI Special Interest Group. Set to
0x14F1.
PCI bus interface status register. The PCI host can monitor its operation using the STATUS field. This
field is further divided into subfields as shown below. These bits can be reset by writing a logic high to
the appropriate bit. See the Status register below for a description of the bits in the register.
PCI bus interface control/command register. The PCI host can configure the SAR bus interface logic
using the COMMAND field. This field is further divided into subfields as shown below. Active HRST*
input causes all bits to be a logic 0. See the Command register below for a description of the bits in the
register.
The CLASS_CODE register is read-only and is used to identify the generic function of the device. See
PCI Bus Specification, Revision 2.1 for the specific allowed settings for this field. Set to 0x020300
(indicates a network controller, specifically an ATM controller).
Revision ID code for the RS8234 chip; 0=Rev A, 1=Rev B, 2=Rev C.
This field identifies the layout of the second part of the predefined header of the PCI Configuration
space (beginning at 0x10). See PCI Bus Specification, Revision 2.1 for the specific possible settings for
this field. Set to 0x00.
Latency timer. Value after HRST* active is 0x00. All bits are writable. The suggested value is 0x10 in
order to allow the complete transfer of a cell.
This read/write register specifies the system cacheline size in units of 32-bit words. Must be initialized
to 0x00 at initialization and reset.
Base address of PCI address space occupied by the RS8234 (as seen and assigned by the host
processor). Value after HRST* active is 0x00. The upper 9 bits are writeable, resulting in an 8 Mbyte
address space.
This register value is used to uniquely identify the add-in board or subsystem where the PCI device
resides. Thus, it provides a mechanism for add-in card vendors to distinguish their cards from one
another even though the cards may have the same PCI controller on them (and therefore the same
DEVICE_ID).
This register value is used to uniquely identify the vendor of an add-in board or subsystem where the
PCI device resides. Thus, it provides a mechanism for add-in card vendors to distinguish their cards
from one another even though the cards can have the same PCI controller on them (and therefore the
same VENDOR_ID).
This field provides an offset into the PCI Configuration space for the location of the first item in the
Capabilities Linked List. Set to 0x50.
This read-only register specifies how often the RS8234 device needs to gain access to the PCI bus,
assuming a clock rate of 33 MHz. Set to 0x02 (a period of time in units of 1/4 microseconds).
This read-only register specifies how long of a burst period the RS8234 device needs to gain access to
the PCI bus. Set to 0x02 (a period of time in units of 1/4 microseconds).
This read-only register tells which interrupt pin the device (or device function) uses. Set to 0x01
(corresponds to interrupt pin INTA#).
Interrupt line identifier. The value in this register tells which input of the system interrupt controller(s)
the device’s interrupt pin is connected to. The device itself does not use this value; rather, it is used by
device drivers and operating systems.
Mindspeed Technologies
Description/Function
™
13.7 PCI Bus Interface Registers
13.0 RS8234 Registers
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