RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 62

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

2.0 Architecture Overview
2.10 Logic Diagram and Pin Descriptions
Table 2-1. Hardware Signal Definitions (2 of 6)
2-30
HINT*
HPERR*
HSERR*
HCLK
HRST*
PCI5V
HLED*
HENUM*
Pin Label
Interrupt Request
Bus Parity Error
System Error
Bus Clock
System Reset
Bus Signalling
LED Power
ENUM#
Signal Name
Mindspeed Technologies
I/O
OD
OD
OD
OD
I/O
I
I
I
Indicates a system error or a parity error on the HAD[31:0]
Signals an interrupt request to the PCI host, and is tied to the
INTA_ line on the PCI bus.
Driven asserted by the RS8234 (as a bus slave) or by a target
addressed by the RS8234 when it acts as a bus master to
indicate a parity error on the HAD[31:0] and HC/BE[3:0]*
lines. It is asserted when the RS8234 is a bus slave or
sampled when the RS8234 is a bus master on the second
clock edge after a valid data phase. The RS8234 drives the
HPERR* line only when acting as a slave.
and HC/BE[3:0]* lines during an address phase. This pin is
handled in the same way as HPERR*, and is only driven by the
RS8234 when it acts as a bus slave.
Supplies the PCI bus clock signal.
Performs a hardware reset of the RS8234 and associated
peripherals when asserted. Must be asserted for 16 cycles of
HCLK.
Must be tied high. This pad has an internal pullup resister to
VDD.
12 mA open drain. Logic low turns on LED. Compact PCI Hot
Swap Signal.
8 mA open drain. Compact PCI Hot Swap Signal.
ATM ServiceSAR Plus with xBR Traffic Management
™
Definition
28234-DSH-001-B
RS8234