RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 247

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

RS8234
ATM ServiceSAR Plus with xBR Traffic Management
10.3.1 Single Read Cycle, Zero Wait State Example
28234-DSH-001-B
Figure 10-2
address cycle (cycle one) at the rising edge of SYSCLK with PCS* and PAS*
active, a memory request is generated by the processor interface circuitry. Also at
this time, the read/write select, bank select, and word select inputs (PWNR,
PBSEL[1:0], and PADDR[1:0]) are internally latched. The byte enables
(PBE[3:0]*) are Don’t-Cares during reads. During cycle two, this local processor
memory request is processed by the memory arbitration circuitry. If no other
memory consumers request an access on the same cycle, the local processor is
granted access on cycle three. However, to take into account bus transceiver
turnaround, cycle three is always a wait or bus recovery state, which gives
sufficient time for the address from the processor to access the SRAM. For zero
wait state SRAM, unless a wait state is inserted by the processor, the data is
available to be latched into the processor on cycle four, which is indicated by the
assertion of PRDY*. Cycle five is an arbitration cycle for the internal memory
consumers, which might have requested access during the processor access. It
also serves as a bus recovery cycle for the processor. Once the PCS*, PAS*,
PWNR, PBSEL[1:0], and PADDR[1:0] are sampled at cycle one, they are
Don’t-Cares for the remainder of the access. DT/R* is an output supplied by the
local processor to indicate the direction of the data transceivers. The RS8234
PDAEN* signal is active to enable data and address.
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illustrates a single read cycle with zero wait states. During the
™
10.0 Local Processor Interface
10.3 Bus Cycle Descriptions
10-5