RS8234EBGC Mindspeed Technologies, RS8234EBGC Datasheet - Page 74

• Manufacturer Part Number: RS8234EBGC
• Description: RS8234EBGC ATM XBR SAR
• Manufacturer: Mindspeed Technologies

3.0 Host Interface
3.3 Write-Only Control and Status
Figure 3-4. Write-Only Control Queue
3-8
READ_UD
3.3.1.3 Underflow
Conditions
WRITE++
Boundary
PCI Bus
submits a new entry, it must first ensure that the SAR has already processed the
entry location. The host compares WRITE to READ_UD. If (WRITE+1) modulo
size_of_queue equals READ_UD, then the host should halt writing to the queue.
This results in being able to use only N-1 queue entries. However, if this is not
done, then a full condition cannot be distinguished from an empty condition. The
host must wait until READ_UD is modified by the SAR before proceeding. This
algorithm ensures that the host does not overflow the control queue, without
reading the queue itself.
increments its write pointer (WRITE++). During this write, the host sets the valid
bit (VLD) in the entry to one.
detected to a specific queue, the SAR attempts to process the queue entry at
READ. Before acting on the entry, the SAR checks for ownership of the entry,
indicated by the VLD bit. Once the RS8234 has processed the entry, it resets the
VLD bit to zero.
An underflow condition occurs when the SAR attempts to retrieve a queue entry
and the host has not yet supplied this entry. This condition only happens on the
free buffer queues. The SAR detects this condition by checking the queue entry
VLD bit. Once detected, the SAR enters an “Underflow Detected” state on this
queue only. Since this signifies that no data buffers are available for reassembly,
the SAR initiates EPD on all channels assigned to this queue.
describes SAR handling of free buffer queue underflow in detail.
The host also maintains a pointer into the queue, WRITE. When the host
Once it has verified its ownership of the entry, the host writes the entry and
The RS8234 “snoops” writes to the control queue areas. Once a write is
READ_UD_PNTR=
VLD
bit
Update Host
Mindspeed Technologies
UPDATE=0
READ
0 0 0 0 0 0 0 0
Y
1
1 1 1 1 1 1 1 1
INTERVAL
UPDATE=
ATM ServiceSAR Plus with xBR Traffic Management
N
1
1
™
1 1 1 1 1 1 1 1 1
(Base Table)
UPDATE++
0 0 0 0
Chapter 5.0
28234-DSH-001-B
READ++
Base
Register
RS8234
100074_014